modelDFFREGL

Edge triggered register bank with low active reset

Extends from DFFREG (Edge triggered register bank with high active reset).

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Clock	Reset	DataOut
*	*	U	U
*	*	0	0
*	0-Trns	1	NC
*	1-Trns	1	DataIn
*	X-Trns	1	X or U or NC
*	*	X	X or U or 0 or NC

  *  = do not care
  U  = L.'U'
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-'
  NC = no change

Clock transition definitions:
  1-Trns: 0 -> 1
  0-Trns: ~ -> 0 or 1 -> * or X -> X|U or U -> X|U
  X-Trns: 0 -> X|U or X|U -> 1

Parameters

Type	Name	Default	Description
SI.Time	tHL (from DFFREG)	0	High->Low delay
SI.Time	tLH (from DFFREG)	0	Low->High delay
D.Interfaces.Strength	strength (from DFFREG)	S.'S_X01'	Output strength
Integer	n (from DFFREG)	1	Data width

Connectors

Type	Name	Default	Description
D.Interfaces.DigitalInput	reset (from DFFREG)
D.Interfaces.DigitalInput	clock (from DFFREG)
D.Interfaces.DigitalInput[n]	dataIn (from DFFREG)
D.Interfaces.DigitalOutput[n]	dataOut (from DFFREG)

Components

Type	Name	Default	Description
Modelica.Electrical.Digital.Delay.InertialDelaySensitiveVector	delay (from DFFREG)
D.Registers.DFFR	dFFR (from DFFREG)

Revisions

September 11, 2009 created by Ulrich Donath