modelDLATREGL
Level sensitive register bank with reset active low
Extends from DLATREG (Level sensitive register bank with reset active high).
Information
Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd
Truth Table
| DataIn | Enable | Reset | DataOut |
| * | * | U | U |
| * | * | 0 | 0 |
| * | 0 | 1 | NC |
| * | 1 | 1 | DataIn |
| * | X | 1 | X or U or NC |
| * | U | ~0 | U |
| * | ~U | X | X or U or 0 or NC |
* = do not care ~ = not equal U = L.'U' 0 = L.'0' or L.'L' 1 = L.'1' or L.'H' X = L.'X' or L.'W' or L.'Z' or L.'-' NC = no change
Parameters
| Type | Name | Default | Description |
|---|---|---|---|
| SI.Time | tHL (from DLATREG) | 0 | High->Low delay |
| SI.Time | tLH (from DLATREG) | 0 | Low->High delay |
| D.Interfaces.Strength | strength (from DLATREG) | S.'S_X01' | Output strength |
| Integer | n (from DLATREG) | 1 | Data width |
Connectors
| Type | Name | Default | Description |
|---|---|---|---|
| D.Interfaces.DigitalInput | reset (from DLATREG) | ||
| D.Interfaces.DigitalInput | enable (from DLATREG) | ||
| D.Interfaces.DigitalInput[n] | dataIn (from DLATREG) | ||
| D.Interfaces.DigitalOutput[n] | dataOut (from DLATREG) |
Components
| Type | Name | Default | Description |
|---|---|---|---|
| D.Delay.InertialDelaySensitiveVector | delay (from DLATREG) | ||
| D.Registers.DLATR | dLATR (from DLATREG) |
Revisions
- September 11, 2009 created by Ulrich Donath