blockUnitDelay

Delay the input by a multiple of the base sample time if discrete block or y=u if continuous block
Diagram of UnitDelay

Extends from Interfaces.PartialSISO_equality (Partial Single Input Single Output (continuous or discrete) control block of Controller library where usually y=u if continuous block).

Information

If discrete block, the output y is sampled and is the value of the sampled input signal u at the previous sample instant, where sample time = sampleClock.sampleTime * sampleFactor and sampleClock.sampleTime is defined globally in the outer component sampleClock and sampleFactor is an Integer parameter of component UnitDelay.

If continuous block, the output y is identical to the input u.

Parameters

TypeNameDefaultDescription
Types.BlockTypeWithGlobalDefaultblockType (from PartialSISO_equality)Modelica_LinearSystems2.Controller.Types.BlockTypeWithGlobalDefault.UseSampleClockOptionType of block
Booleancontinuous (from PartialSISO_equality)blockType == Types.BlockTypeWithGlobalDefault.Continuous or blockType == Types.BlockTypeWithGlobalDefault.UseSampleClockOption and sampleClock.blockType == Types.BlockType.ContinuousTrue, if continuous block, otherwise discrete block
Discrete block parameters
IntegersampleFactor (from PartialSISO_equality)1Sample factor for sample time (Ts = sampleFactor * sampleClock.sampleTime)

Connectors

TypeNameDefaultDescription
Modelica.Blocks.Interfaces.RealInputu (from PartialSISO_equality)Continuous or discrete input signal of block
Modelica.Blocks.Interfaces.RealOutputy (from PartialSISO_equality)Continuous or discrete output signal of block