modelFourthOrder_AVRII_Discrete

5-bus system with 4th-order machine and AVRTypeII_Discrete
Diagram of FourthOrder_AVRII_Discrete

Extends from Modelica.Icons.Example (Icon for runnable examples), OpenIPSL.Examples.PSATSystems.TwoAreaOld.BaseClasses.BaseOrder4 (Template for base network and a 4th order generator).

Information

Simulate for 20 seconds. Variables of interest are:

  • aVRTypeII.vf

Compare these results with the ones from the other example systems within the Discretization subpackage.

Components

TypeNameDefaultDescription
OpenIPSL.Electrical.Buses.Busbus1 (from BaseNetwork)
OpenIPSL.Electrical.Buses.Busbus2 (from BaseNetwork)
OpenIPSL.Electrical.Buses.Busbus3 (from BaseNetwork)
OpenIPSL.Electrical.Buses.Busbus4 (from BaseNetwork)
OpenIPSL.Electrical.Buses.Busbus5 (from BaseNetwork)
OpenIPSL.Electrical.Branches.PwLineline_1_4 (from BaseNetwork)
OpenIPSL.Electrical.Branches.PwLineline_4_3 (from BaseNetwork)
OpenIPSL.Electrical.Branches.PwLineline_3_5 (from BaseNetwork)
OpenIPSL.Electrical.Branches.PwLineline_5_2 (from BaseNetwork)
OpenIPSL.Electrical.Events.PwFaultpwFault (from BaseNetwork)
OpenIPSL.Electrical.Machines.PSAT.Order2order2 (from BaseNetwork)
OpenIPSL.Electrical.SystemBaseSysData (from BaseNetwork)
OpenIPSL.Electrical.Machines.PSAT.Order4order4 (from BaseOrder4)
DiscreteAVR.AVRTypeII_discreteaVRTypeII
Modelica.Blocks.Sources.Constantvref2
Modelica.Clocked.RealSignals.Sampler.Holdhold1
Modelica.Clocked.RealSignals.Sampler.Samplesample1
Modelica.Clocked.RealSignals.Sampler.SampleClockedsample2
Modelica.Clocked.ClockSignals.Clocks.PeriodicRealClockperiodicClock1